For System on Chip(SoC) ASIC and other types of designs the Central Processing Unit (CPU), Digital Signal Processor (DSP), memory and other related circuits are integrated within a single ASIC package. The trend is towards providing more data streams, requiring more data processing to occur. The design of the CPU and the DSP typically places the control stream (program data) and the data stream on the same bus, where these various types of data share bus cycles. The data stream can include, for example, operands and the results of computations, as well data transferred between interfaces and memory under the control of a direct memory access (DMA) controller. However, more data streams require more bus cycles, which in turn reduces the control stream bus cycles, and thus reduces the number of instructions executed per second by the CPU and the DSP (typically measured in millions of instructions per second, or MIPS). The reduction in the number of MIPs is very undesirable, as modern data processing systems are typically expected to execute more instructions per second. This can be especially true in the SoC type systems, where the SoC system may operate within a wireless communicator such as cellular telephone, and be required to execute in real time or near real time a number of complex speech and/or packet data and/or signaling operations and algorithms, including encryption and decryption operations and algorithms.
While it may appear that simply increasing the clock frequency would enable one to increase the number of MIPs, in reality an increase in the clock frequency requires an increase in operating current. In battery powered and portable device applications any increase in current consumption is generally seen as a disadvantage, as the time between required rechargings of the battery is reduced.
A need thus exists to increase the number of MIPs in a data processing system, in particular in a SoC type system, without also significantly increasing the current consumption.